Lightweight Hardware Transform Design for the Versatile Video Coding 4K ASIC Decoders

Versatile Video Coding (VVC) is the next generation video coding standard finalized in July 2020. VVC introduces new tools enhancing efficiency compared to its predecessor High Efficiency (HEVC). These have a significant impact on software decoder complexity estimated 2 times HEVC complexity. In particular, transform module includes separable and non-separable transforms named Multiple Transform Selection (MTS) Low Frequency Non-Separable (LFNST) tools, respectively. this paper, we present an area-efficient hardware architecture of inverse for decoder. The proposed design uses total 64 regular multipliers pipelined targeting Application-Specific Integrated Circuit (ASIC) platforms. It consists multi-standard that supports modules recent MPEG standards including Advanced (AVC), VVC. leverages all primary secondary transforms’ optimisations butterfly decomposition, coefficients zeroing inherent linear relationship between transforms. synthesized results show method sustains constant throughput 1 sample per cycle latency block sizes. operates at 600 MHz frequency enabling decode real-time 4K 30 frames second 4:2:2 chroma sub-sampling format. has been integrated ASIC UHD energy-aware decoding videos consumer devices.